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Integrated Circuit Systems, Inc.
ICS9179-03
Low Skew Fan Out Buffers
General Description
The ICS9179-03 generates low skew clock buffers required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. Outputs will handle up to 133MHz clocks. An output enable is provided for testability. The device is a buffer with low output to output skew. This is a Fanout buffer device, not using an internal PLL. This buffer can also be a feedback to an external PLL stage for phase synchronization to a master clock. There are a total of ten outputs, sufficient for feedback to a PLL source and to drive four small outline DIMM modules (S.O. DIMM) at 2 clocks each. Or a total of ten outputs as a Fanout buffer from a common clock source. The individual clock outputs are addressable through I2C to be enabled, or stopped in a low state for reduced EMI when the lines are not needed.
Features

Ten High speed, low noise non-inverting buffers for (to 133MHz), clock buffer applications. Output slew rate faster than 1.5V/ns into 20pF Supports up to four small outline DIMMS (S.O. DIMM). Synchronous clocks skew matched to 250 ps window on OUTPUTs (0:9). I2C Serial Configuration interface to allow individual OUTPUTs to be stopped low. Multiple VDD, VSS pins for noise reduction Tri-state pin for testing 3.0V 3.7V supply range 28-pin (209 mil) SSOP and (6.1mm) TSSOP package
Block Diagram
Pin Configuration
28-Pin SSOP & TSSOP
PentiumPro is a trademark of Intel Corporation I2C is a trademark of Philips Corporation 9179-03 Rev H 10/16/00
ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9179-03
Pin Descriptions
PIN NUMBER 2, 3 6, 7 22, 23 26, 27 11 18 9 20 14 15 1, 5, 10, 19, 24, 28 4, 8, 12, 16, 17, 21, 25 13 16 P I N NA M E OUTPUT (0:1) OUTPUT (2:3) OUTPUT (4:5) OUTPUT (6:7) OUTPUT8 OUTPUT9 BU F _ I N OE SDATA SCLK VDD (0:5) GND (0:5) VDDI GNDI TYPE OUT OUT OUT OUT OUT OUT IN IN I/O I/O PWR PWR PWR PWR DESCRIPTION C l o c k o u t p u t s 1, u s e s V D D 0 , G N D 0 C l o c k o u t p u t s 1, u s e s V D D 1 , G N D 1 Clock outputs1 uses VDD2, GND2 Clock output1 uses VDD3, GND3 Clock output1 uses VDD4, GND4 Clock output1 uses VDD5, GND5 Input for buffers Tri-states all outputs when held LOW. Has internal pull-up.2 D a t a p i n f o r I 2C c i r c u i t r y 3 C l o c k p i n f o r I 2C c i r c u i t r y 3 3.3V Power supply for OUTPUT buffers Ground for OUTPUT buffers 3.3V Power supply for I2C circuitry and internal logic G r o u n d f o r I 2C c i r c u i t r y a n d i n t e r n a l l o g i c
Notes: 1. At power up all ten OUTPUTs are enabled and active. 2. OE has a 100K Ohm internal pull-up resistor to keep all outputs active. 3. The SDATA and SCLK inputs both also have internal pull-up resistors with values above 100K Ohms as well for complete platform flexibility.
Power Groups
VDD (0:5), GND (0:5) = Power supply for OUTPUT buffer VDDI, GNDI = Power supply for I2C circuitry
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ICS9179-03
Technical Pin Function Descriptions
VDD This is the power supply to the internal core logic of the device as well as the clock output buffers for OUTPUT (0:9). This pin operates at 3.3V volts. Clocks from the listed buffers that it supplies will have a voltage swing from Ground to this level. For the actual guaranteed high and low voltage levels for the Clocks, please consult the DC parameter table in this data sheet. GND This is the power supply ground (common or negative) return pin for the internal core logic and all the output buffers. OUTPUT (0:9) These Output Clocks are use to drive Dynamic RAMs and are low skew copies of the CPU Clocks. The voltage swing of the OUTPUTs output is controlled by the supply voltage that is applied to VDD of the device, operates at 3.3 volts. I2C The SDATA and SCLOCK Inputs are use to program the device. The clock generator is a slave-receiver device in the I2C protocol. It will allow read-back of the registers. See configuration map for register functions. The I2C specification in Philips I2C Peripherals Data Handbook (1996) should be followed. BUF_IN Input for Fanout buffers (OUTPUT 0:9). OE OE tristates all outputs when held low. VDD1 This is the power supply to I2C circuitry.
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ICS9179-03
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
General I2C serial interface information
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit ICS (Slave/Receiver)
How to Read:
Controller (host) will send start bit. Controler (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 6 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit

How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK Stop Bit
Notes:
1. 2. 3. 4. 5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
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ICS9179-03
Serial Configuration Command Bitmaps
Byte 0: OUTPUT Clock Register (Default=0)
BIT Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 PIN# 7 6 3 2 PWD 1 1 1 1 1 1 1 1 DESCRIPTION R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d OUTPUT3 OUTPUT2 OUTPUT1 OUTPUT0
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default Byte 1: OUTPUT Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 27 26 23 22 PWD 1 1 1 1 1 1 1 1 DESCRIPTION OUTPUT7 (Act/Inact) OUTPUT6 (Act/Inact) OUTPUT5 (Act/Inact) OUTPUT4 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Byte 2: OUTPUT Clock Register
BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PIN# 18 11 PWD 1 1 1 1 1 1 1 1 DESCRIPTION OUTPUT9 (Act/Inact) OUTPUT8 (Act/Inact) R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d R e s e r ve d
Notes: 1 = Enabled; 0 = Disabled, outputs held low
Note: PWD = Power-Up Default
Notes: 1 = Enabled; 0 = Disabled, outputs held low
ICS9179-03 Power Management
The values below are estimates of target specifications.
Condition Max 3.3V supply consumption Max discrete cap loads VDD = 3.465V All static inputs = VDD or GND 3mA
No Clock Mode (BUF_IN - VDD1 or GND) I2C Circuitry Active Active 66MHz (BUF_IN = 66.66MHz) Active 100MHz (BUF_IN = 100.00MHz) Active 133MHz (BUF_IN = 133.33MHz)
Functionality
230mA 360mA 460mA
OE# 0 1
OUTPUT (0:9) Hi-Z 1 X BUF_IN
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ICS9179-03
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to VDD +0.5 V Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
PARAM ETER Input High Voltage Input Low Voltage Input High Current Input Low Current
Operating Supply Current
SYM BOL VIH VIL IIH IIL IIL IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 Fi 1 C IN1
CONDITIONS
M IN 2 VSS -0.3 -5 -60
TYP
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with 100K pull-up resistors C L = 0 pF; FIN @ 66M C L = 0 pF; FIN @ 100M C L = 0 pF; FIN @ 133M C L = 30 pF; RS=33; FIN @ 66M C L = 30 pF; RS=33; FIN @ 100M C L = 30 pF; RS=33; FIN @ 133M VDD = 3.3 V; All Outputs Loaded Logic Inputs
-33 80 120 170 180 240 350
M AX UNITS VDD+0.3 V 0.8 V 5 uA uA uA 120 mA 180 mA 240 mA 260 mA 360 mA 460 mA 133 5 M Hz pF
Input frequency Input Capacitance
1
10
Guarenteed by design, not 100% tested in production.
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ICS9179-03
Electrical Characteristics - Outputs
T A = 0 - 70C; V DD = 3.3 V +/-5%; C L = 20 - 30 pF (unless otherwise stated) PARAM ETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 1 Fall Time 1 Duty Cycle 1 Skew1 SYM BOL R DSP R DSN VOH VOL IOH IOL Tr Tf Dt Ts k T PHL1 T PLH1 T PHL2 T PLH2 T EN T DIS CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -30 mA IOL = 23 mA VOH = 2.0 V VOL = 0.8 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 50% Buffer In to 90% Out 50% Buffer In to 10% Out VT = 1.5 V VT = 1.5 V 45 1 1 1 1 1 1 M IN 10 10 2.3 TYP M AX 24 24 0.4 -54 1.33 1.33 55 250 5.5 5.5 5 5 8 8 UNITS V V mA mA ns ns % ps ns ns ns ns ns ns
40
3 0.27 -115 57 0.95 0.95 50 110 5.2 5.2 4.3 4.3
Propagation 1 ,2
Note1: Paramater is guaranteed by design and characterization for all operating frequencies, (10M Hz - 133M Hz). Not 100% tested in production Note2: Duty cycle of input clock is 47.5% to 52.5%. Input edge rate is for propagation delay 1V/ns
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ICS9179-03
General Layout Precautions: 1) Use a ground plane on the top layer of the PCB in all areas not used by traces. 2) Make all power traces and vias as wide as possible to lower inductance.
Notes: 1 All clock outputs should have series terminating resistor. Not shown in all places to improve readibility of diagram 2 Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs.
Capacitor Values: All unmarked capacitors are 0.01F ceramic
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ICS9179-03
Ordering Information
Example:
ICS9179yF-03-T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
ICS XXXX y F - PPP - T
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
ICS9179-03
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 0.05 0.80 0.19 1.20 0.15 1.05 0.30 .002 .032 .007 .047 .006 .041 .012
A A1 A2 b c D E E1 e L N aaa VARIATIONS N
0.09 0.20 SEE VARIATIONS 8.10 BASIC 6.00 6.20
.0035 .008 SEE VARIATIONS 0.319 .236 .244 0.0256 BASIC .018 .030 SEE VARIATIONS 0 8 .004
0.65 BASIC 0.45 0.75 SEE VARIATIONS 0 8 0.10
D mm. MIN 9.60 MAX 9.80 MIN .378
D (inch) MAX .386
7/6/00 Rev B
6.10 mm. Body, 0.65 mm. pitch TSSOP (0.0256 mil) (240 mil)
28
MO-153 JEDEC Doc.# 10-0038
Ordering Information
ICS9179yG-03-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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